/*
 * File   : top_bench.v
 * Date   : 20171106
 * Author : Bibo Yang, rspwfpgas@163.com
 *
 */

`timescale 1ns/1ns
module top_bench();

// CLK

// RST

// MAIN
reg phy_giga_mode;
reg phy_link_up;
initial                                                
begin                                             
    $display("Testbench running!");
	
	top_bench.phy_giga_mode = 1'b1;
	top_bench.phy_link_up   = 1'b0;
	#2000;
	top_bench.phy_link_up   = 1'b1;
end

// PHY RGMII: signal naming from DUT point of view
wire       RxClk;
wire       RxDv;
wire [3:0] RxData;
wire       TxClk;
wire       TxEn;
wire [3:0] TxData;
phy_rgmii_bfm bfm_rgmii (
    .RxClk  (RxClk),
    .RxDv   (RxDv),
    .RxData (RxData),
    .TxClk  (TxClk),
    .TxEn   (TxEn),
    .TxData (TxData)
);
//// RGMII loopback for BFM
//assign {TxClk, TxEn, TxData} = {RxClk, RxDv, RxData};

// DUT
mac_top dut (
    .RxClk  (RxClk),
    .RxDv   (RxDv),
    .RxData (RxData),
    .TxClk  (TxClk),
    .TxEn   (TxEn),
    .TxData (TxData)
);

endmodule

